//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.1 (win64) Build 2188600 Wed Apr  4 18:40:38 MDT 2018
//Date        : Thu Nov 12 11:46:46 2020
//Host        : SPV8WKHHEF4QG0W running 64-bit Service Pack 1  (build 7601)
//Command     : generate_target design_1_wrapper.bd
//Design      : design_1_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
   (APB_M_paddr,
    APB_M_penable,
    APB_M_prdata,
    APB_M_pready,
    APB_M_psel,
    APB_M_pslverr,
    APB_M_pwdata,
    APB_M_pwrite,
    B_aux_rx_io_n_1,
    B_aux_rx_io_p_1,
    B_dp159_iic_1_scl_io,
    B_dp159_iic_1_sda_io,
    GPIO_Out,
    IIC_0_scl_io,
    IIC_0_sda_io,
    IIC_MAIN_scl_io,
    IIC_MAIN_sda_io,
    I_mgtrefclk0_n_in_1,
    I_mgtrefclk0_p_in_1,
    I_mgtrefclk1_n_in_1,
    I_mgtrefclk1_p_in_1,
    I_osc_clk,
    I_phy_rxn_0,
    I_phy_rxn_1,
    I_phy_rxp_0,
    I_phy_rxp_1,
    O_dp159_rst_1,
    O_rx_bpc_1,
    O_rx_cformat_1,
    O_rx_hpd_1,
    O_rx_vid_msa_hres_1,
    O_rx_vid_pixel_mode_1,
    O_rx_vid_stream_1_tx_vid_enable,
    O_rx_vid_stream_1_tx_vid_hsync,
    O_rx_vid_stream_1_tx_vid_oddeven,
    O_rx_vid_stream_1_tx_vid_pixel0,
    O_rx_vid_stream_1_tx_vid_pixel1,
    O_rx_vid_stream_1_tx_vid_pixel2,
    O_rx_vid_stream_1_tx_vid_pixel3,
    O_rx_vid_stream_1_tx_vid_vsync,
    aux_rx_io_n,
    aux_rx_io_p,
    aux_tx_io_n,
    aux_tx_io_n_0,
    aux_tx_io_p,
    aux_tx_io_p_0,
    clk_100,
    clk_200,
//	clk_bl_125,
//	clk_ddr_ref_200,
    clk_out0,
    clk_out1,
    dp159_IIC_scl_io,
    dp159_IIC_sda_io,
    dp159_OE,
    locked,
    mgtrefclk0_pad_n_in,
    mgtrefclk0_pad_p_in,
    mgtrefclk1_pad_n_in,
    mgtrefclk1_pad_p_in,
    peripheral_aresetn1,
    phy_txn_out,
    phy_txn_out_0,
    phy_txp_out,
    phy_txp_out_0,
    rx_bpc,
    rx_cformat,
    rx_hpd,
    rx_vid_msa_hres,
    rx_vid_pixel_mode,
    rx_vid_stream1_tx_vid_enable,
    rx_vid_stream1_tx_vid_hsync,
    rx_vid_stream1_tx_vid_oddeven,
    rx_vid_stream1_tx_vid_pixel0,
    rx_vid_stream1_tx_vid_pixel1,
    rx_vid_stream1_tx_vid_pixel2,
    rx_vid_stream1_tx_vid_pixel3,
    rx_vid_stream1_tx_vid_vsync,
    sys_rst,
    tx_hpd,
//	DP1_tx_link_clk,
//	tx_hpd_0,
    tx_video_stream0_tx_vid_enable,
    tx_video_stream0_tx_vid_hsync,
    tx_video_stream0_tx_vid_oddeven,
    tx_video_stream0_tx_vid_pixel0,
    tx_video_stream0_tx_vid_pixel1,
    tx_video_stream0_tx_vid_pixel2,
    tx_video_stream0_tx_vid_pixel3,
    tx_video_stream0_tx_vid_vsync,
    tx_video_stream1_tx_vid_enable,
    tx_video_stream1_tx_vid_hsync,
    tx_video_stream1_tx_vid_oddeven,
    tx_video_stream1_tx_vid_pixel0,
    tx_video_stream1_tx_vid_pixel1,
    tx_video_stream1_tx_vid_pixel2,
    tx_video_stream1_tx_vid_pixel3,
    tx_video_stream1_tx_vid_vsync);
  output [31:0]APB_M_paddr;
  output APB_M_penable;
  input [31:0]APB_M_prdata;
  input [0:0]APB_M_pready;
  output [0:0]APB_M_psel;
  input [0:0]APB_M_pslverr;
  output [31:0]APB_M_pwdata;
  output APB_M_pwrite;
  inout B_aux_rx_io_n_1;
  inout B_aux_rx_io_p_1;
  inout B_dp159_iic_1_scl_io;
  inout B_dp159_iic_1_sda_io;
  output [31:0]GPIO_Out;
  inout IIC_0_scl_io;
  inout IIC_0_sda_io;
  inout IIC_MAIN_scl_io;
  inout IIC_MAIN_sda_io;
  input I_mgtrefclk0_n_in_1;
  input I_mgtrefclk0_p_in_1;
  input I_mgtrefclk1_n_in_1;
  input I_mgtrefclk1_p_in_1;
  input I_osc_clk;
  input [3:0]I_phy_rxn_0;
  input [3:0]I_phy_rxn_1;
  input [3:0]I_phy_rxp_0;
  input [3:0]I_phy_rxp_1;
  output [0:0]O_dp159_rst_1;
  output [2:0]O_rx_bpc_1;
  output [2:0]O_rx_cformat_1;
  output O_rx_hpd_1;
  output [15:0]O_rx_vid_msa_hres_1;
  output [2:0]O_rx_vid_pixel_mode_1;
  output O_rx_vid_stream_1_tx_vid_enable;
  output O_rx_vid_stream_1_tx_vid_hsync;
  output O_rx_vid_stream_1_tx_vid_oddeven;
  output [47:0]O_rx_vid_stream_1_tx_vid_pixel0;
  output [47:0]O_rx_vid_stream_1_tx_vid_pixel1;
  output [47:0]O_rx_vid_stream_1_tx_vid_pixel2;
  output [47:0]O_rx_vid_stream_1_tx_vid_pixel3;
  output O_rx_vid_stream_1_tx_vid_vsync;
  inout aux_rx_io_n;
  inout aux_rx_io_p;
  inout aux_tx_io_n;
  inout aux_tx_io_n_0;
  inout aux_tx_io_p;
  inout aux_tx_io_p_0;
  output clk_100;
  output clk_200;
//  output clk_bl_125;
//  output clk_ddr_ref_200;
  output clk_out0;
  output clk_out1;
  inout dp159_IIC_scl_io;
  inout dp159_IIC_sda_io;
  output [0:0]dp159_OE;
  output locked;
  input mgtrefclk0_pad_n_in;
  input mgtrefclk0_pad_p_in;
  input mgtrefclk1_pad_n_in;
  input mgtrefclk1_pad_p_in;
  output [0:0]peripheral_aresetn1;
  output [3:0]phy_txn_out;
  output [3:0]phy_txn_out_0;
  output [3:0]phy_txp_out;
  output [3:0]phy_txp_out_0;
  output [2:0]rx_bpc;
  output [2:0]rx_cformat;
  output rx_hpd;
  output [15:0]rx_vid_msa_hres;
  output [2:0]rx_vid_pixel_mode;
  output rx_vid_stream1_tx_vid_enable;
  output rx_vid_stream1_tx_vid_hsync;
  output rx_vid_stream1_tx_vid_oddeven;
  output [47:0]rx_vid_stream1_tx_vid_pixel0;
  output [47:0]rx_vid_stream1_tx_vid_pixel1;
  output [47:0]rx_vid_stream1_tx_vid_pixel2;
  output [47:0]rx_vid_stream1_tx_vid_pixel3;
  output rx_vid_stream1_tx_vid_vsync;
  input sys_rst;
  input tx_hpd;
//  output DP1_tx_link_clk;
//  input tx_hpd_0;
  input tx_video_stream0_tx_vid_enable;
  input tx_video_stream0_tx_vid_hsync;
  input tx_video_stream0_tx_vid_oddeven;
  input [47:0]tx_video_stream0_tx_vid_pixel0;
  input [47:0]tx_video_stream0_tx_vid_pixel1;
  input [47:0]tx_video_stream0_tx_vid_pixel2;
  input [47:0]tx_video_stream0_tx_vid_pixel3;
  input tx_video_stream0_tx_vid_vsync;
  input tx_video_stream1_tx_vid_enable;
  input tx_video_stream1_tx_vid_hsync;
  input tx_video_stream1_tx_vid_oddeven;
  input [47:0]tx_video_stream1_tx_vid_pixel0;
  input [47:0]tx_video_stream1_tx_vid_pixel1;
  input [47:0]tx_video_stream1_tx_vid_pixel2;
  input [47:0]tx_video_stream1_tx_vid_pixel3;
  input tx_video_stream1_tx_vid_vsync;

  wire [31:0]APB_M_paddr;
  wire APB_M_penable;
  wire [31:0]APB_M_prdata;
  wire [0:0]APB_M_pready;
  wire [0:0]APB_M_psel;
  wire [0:0]APB_M_pslverr;
  wire [31:0]APB_M_pwdata;
  wire APB_M_pwrite;
  wire B_aux_rx_io_n_1;
  wire B_aux_rx_io_p_1;
  wire B_dp159_iic_1_scl_i;
  wire B_dp159_iic_1_scl_io;
  wire B_dp159_iic_1_scl_o;
  wire B_dp159_iic_1_scl_t;
  wire B_dp159_iic_1_sda_i;
  wire B_dp159_iic_1_sda_io;
  wire B_dp159_iic_1_sda_o;
  wire B_dp159_iic_1_sda_t;
  wire [31:0]GPIO_Out;
  wire IIC_0_scl_i;
  wire IIC_0_scl_io;
  wire IIC_0_scl_o;
  wire IIC_0_scl_t;
  wire IIC_0_sda_i;
  wire IIC_0_sda_io;
  wire IIC_0_sda_o;
  wire IIC_0_sda_t;
  wire IIC_MAIN_scl_i;
  wire IIC_MAIN_scl_io;
  wire IIC_MAIN_scl_o;
  wire IIC_MAIN_scl_t;
  wire IIC_MAIN_sda_i;
  wire IIC_MAIN_sda_io;
  wire IIC_MAIN_sda_o;
  wire IIC_MAIN_sda_t;
  wire I_mgtrefclk0_n_in_1;
  wire I_mgtrefclk0_p_in_1;
  wire I_mgtrefclk1_n_in_1;
  wire I_mgtrefclk1_p_in_1;
  wire I_osc_clk;
  wire [3:0]I_phy_rxn_0;
  wire [3:0]I_phy_rxn_1;
  wire [3:0]I_phy_rxp_0;
  wire [3:0]I_phy_rxp_1;
  wire [0:0]O_dp159_rst_1;
  wire [2:0]O_rx_bpc_1;
  wire [2:0]O_rx_cformat_1;
  wire O_rx_hpd_1;
  wire [15:0]O_rx_vid_msa_hres_1;
  wire [2:0]O_rx_vid_pixel_mode_1;
  wire O_rx_vid_stream_1_tx_vid_enable;
  wire O_rx_vid_stream_1_tx_vid_hsync;
  wire O_rx_vid_stream_1_tx_vid_oddeven;
  wire [47:0]O_rx_vid_stream_1_tx_vid_pixel0;
  wire [47:0]O_rx_vid_stream_1_tx_vid_pixel1;
  wire [47:0]O_rx_vid_stream_1_tx_vid_pixel2;
  wire [47:0]O_rx_vid_stream_1_tx_vid_pixel3;
  wire O_rx_vid_stream_1_tx_vid_vsync;
  wire aux_rx_io_n;
  wire aux_rx_io_p;
  wire aux_tx_io_n;
  wire aux_tx_io_n_0;
  wire aux_tx_io_p;
  wire aux_tx_io_p_0;
  wire clk_100;
  wire clk_200;
  wire clk_out0;
  wire clk_out1;
  wire dp159_IIC_scl_i;
  wire dp159_IIC_scl_io;
  wire dp159_IIC_scl_o;
  wire dp159_IIC_scl_t;
  wire dp159_IIC_sda_i;
  wire dp159_IIC_sda_io;
  wire dp159_IIC_sda_o;
  wire dp159_IIC_sda_t;
  wire [0:0]dp159_OE;
  wire locked;
  wire mgtrefclk0_pad_n_in;
  wire mgtrefclk0_pad_p_in;
  wire mgtrefclk1_pad_n_in;
  wire mgtrefclk1_pad_p_in;
  wire [0:0]peripheral_aresetn1;
  wire [3:0]phy_txn_out;
  wire [3:0]phy_txn_out_0;
  wire [3:0]phy_txp_out;
  wire [3:0]phy_txp_out_0;
  wire [2:0]rx_bpc;
  wire [2:0]rx_cformat;
  wire rx_hpd;
  wire [15:0]rx_vid_msa_hres;
  wire [2:0]rx_vid_pixel_mode;
  wire rx_vid_stream1_tx_vid_enable;
  wire rx_vid_stream1_tx_vid_hsync;
  wire rx_vid_stream1_tx_vid_oddeven;
  wire [47:0]rx_vid_stream1_tx_vid_pixel0;
  wire [47:0]rx_vid_stream1_tx_vid_pixel1;
  wire [47:0]rx_vid_stream1_tx_vid_pixel2;
  wire [47:0]rx_vid_stream1_tx_vid_pixel3;
  wire rx_vid_stream1_tx_vid_vsync;
  wire sys_rst;
  wire tx_hpd;
//  wire tx_hpd_0;
  wire tx_video_stream0_tx_vid_enable;
  wire tx_video_stream0_tx_vid_hsync;
  wire tx_video_stream0_tx_vid_oddeven;
  wire [47:0]tx_video_stream0_tx_vid_pixel0;
  wire [47:0]tx_video_stream0_tx_vid_pixel1;
  wire [47:0]tx_video_stream0_tx_vid_pixel2;
  wire [47:0]tx_video_stream0_tx_vid_pixel3;
  wire tx_video_stream0_tx_vid_vsync;
  wire tx_video_stream1_tx_vid_enable;
  wire tx_video_stream1_tx_vid_hsync;
  wire tx_video_stream1_tx_vid_oddeven;
  wire [47:0]tx_video_stream1_tx_vid_pixel0;
  wire [47:0]tx_video_stream1_tx_vid_pixel1;
  wire [47:0]tx_video_stream1_tx_vid_pixel2;
  wire [47:0]tx_video_stream1_tx_vid_pixel3;
  wire tx_video_stream1_tx_vid_vsync;
  
  (*mark_debug = "true"*) wire [31:0]   tx_lane0_tdata   ;
  (*mark_debug = "true"*) wire          tx_lane0_tready  ;
  (*mark_debug = "true"*) wire [11:0]   tx_lane0_tuser   ;
  (*mark_debug = "true"*) wire          tx_lane0_tvalid  ;
  
  
  (*mark_debug = "true"*)wire       DP1_axi4s_rstn  ;
  (*mark_debug = "true"*)wire       DP1_phy_rstn    ;
  (*mark_debug = "true"*)wire       DP1_sb_aclk     ;
  (*mark_debug = "true"*)wire [31:0]DP1_tx_data     ;
  (*mark_debug = "true"*)wire [31:0]DP1_tx_data1    ;
  (*mark_debug = "true"*)wire [31:0]DP1_tx_data2    ;
  (*mark_debug = "true"*)wire [31:0]DP1_tx_data3    ;
//  (*mark_debug = "true"*)wire       DP1_tx_link_clk ;
  (*mark_debug = "true"*)wire       DP1_tx_ready    ;
  (*mark_debug = "true"*)wire       DP1_tx_ready1   ;
  (*mark_debug = "true"*)wire       DP1_tx_ready2   ;
  (*mark_debug = "true"*)wire       DP1_tx_ready3   ;
  (*mark_debug = "true"*)wire [11:0]DP1_tx_user     ;
  (*mark_debug = "true"*)wire [11:0]DP1_tx_user1    ;
  (*mark_debug = "true"*)wire [11:0]DP1_tx_user2    ;
  (*mark_debug = "true"*)wire [11:0]DP1_tx_user3    ;
  (*mark_debug = "true"*)wire       DP1_tx_valid    ;
  (*mark_debug = "true"*)wire       DP1_tx_valid1   ;
  (*mark_debug = "true"*)wire       DP1_tx_valid2   ;
  (*mark_debug = "true"*)wire       DP1_tx_valid3   ;
  
  
  
  
  

  IOBUF B_dp159_iic_1_scl_iobuf
       (.I(B_dp159_iic_1_scl_o),
        .IO(B_dp159_iic_1_scl_io),
        .O(B_dp159_iic_1_scl_i),
        .T(B_dp159_iic_1_scl_t));
  IOBUF B_dp159_iic_1_sda_iobuf
       (.I(B_dp159_iic_1_sda_o),
        .IO(B_dp159_iic_1_sda_io),
        .O(B_dp159_iic_1_sda_i),
        .T(B_dp159_iic_1_sda_t));
  IOBUF IIC_0_scl_iobuf
       (.I(IIC_0_scl_o),
        .IO(IIC_0_scl_io),
        .O(IIC_0_scl_i),
        .T(IIC_0_scl_t));
  IOBUF IIC_0_sda_iobuf
       (.I(IIC_0_sda_o),
        .IO(IIC_0_sda_io),
        .O(IIC_0_sda_i),
        .T(IIC_0_sda_t));
  IOBUF IIC_MAIN_scl_iobuf
       (.I(IIC_MAIN_scl_o),
        .IO(IIC_MAIN_scl_io),
        .O(IIC_MAIN_scl_i),
        .T(IIC_MAIN_scl_t));
  IOBUF IIC_MAIN_sda_iobuf
       (.I(IIC_MAIN_sda_o),
        .IO(IIC_MAIN_sda_io),
        .O(IIC_MAIN_sda_i),
        .T(IIC_MAIN_sda_t));
//  design_1 design_1_i
  design_1 dp_core
  		(.APB_M_paddr(APB_M_paddr),
        .APB_M_penable(APB_M_penable),
        .APB_M_prdata(APB_M_prdata),
        .APB_M_pready(APB_M_pready),
        .APB_M_psel(APB_M_psel),
        .APB_M_pslverr(APB_M_pslverr),
        .APB_M_pwdata(APB_M_pwdata),
        .APB_M_pwrite(APB_M_pwrite),
        .B_aux_rx_io_n_1(B_aux_rx_io_n_1),
        .B_aux_rx_io_p_1(B_aux_rx_io_p_1),
        .B_dp159_iic_1_scl_i(B_dp159_iic_1_scl_i),
        .B_dp159_iic_1_scl_o(B_dp159_iic_1_scl_o),
        .B_dp159_iic_1_scl_t(B_dp159_iic_1_scl_t),
        .B_dp159_iic_1_sda_i(B_dp159_iic_1_sda_i),
        .B_dp159_iic_1_sda_o(B_dp159_iic_1_sda_o),
        .B_dp159_iic_1_sda_t(B_dp159_iic_1_sda_t),
        .GPIO_Out(GPIO_Out),
        .IIC_0_scl_i(IIC_0_scl_i),
        .IIC_0_scl_o(IIC_0_scl_o),
        .IIC_0_scl_t(IIC_0_scl_t),
        .IIC_0_sda_i(IIC_0_sda_i),
        .IIC_0_sda_o(IIC_0_sda_o),
        .IIC_0_sda_t(IIC_0_sda_t),
        .IIC_MAIN_scl_i(IIC_MAIN_scl_i),
        .IIC_MAIN_scl_o(IIC_MAIN_scl_o),
        .IIC_MAIN_scl_t(IIC_MAIN_scl_t),
        .IIC_MAIN_sda_i(IIC_MAIN_sda_i),
        .IIC_MAIN_sda_o(IIC_MAIN_sda_o),
        .IIC_MAIN_sda_t(IIC_MAIN_sda_t),
        .I_mgtrefclk0_n_in_1(I_mgtrefclk0_n_in_1),
        .I_mgtrefclk0_p_in_1(I_mgtrefclk0_p_in_1),
        .I_mgtrefclk1_n_in_1(I_mgtrefclk1_n_in_1),
        .I_mgtrefclk1_p_in_1(I_mgtrefclk1_p_in_1),
        .I_osc_clk(I_osc_clk),
        .I_phy_rxn_0(I_phy_rxn_0),
        .I_phy_rxn_1(I_phy_rxn_1),
        .I_phy_rxp_0(I_phy_rxp_0),
        .I_phy_rxp_1(I_phy_rxp_1),
        .O_dp159_rst_1(O_dp159_rst_1),
        .O_rx_bpc_1(O_rx_bpc_1),
        .O_rx_cformat_1(O_rx_cformat_1),
        .O_rx_hpd_1(O_rx_hpd_1),
        .O_rx_vid_msa_hres_1(O_rx_vid_msa_hres_1),
        .O_rx_vid_pixel_mode_1(O_rx_vid_pixel_mode_1),
        .O_rx_vid_stream_1_tx_vid_enable(O_rx_vid_stream_1_tx_vid_enable),
        .O_rx_vid_stream_1_tx_vid_hsync(O_rx_vid_stream_1_tx_vid_hsync),
        .O_rx_vid_stream_1_tx_vid_oddeven(O_rx_vid_stream_1_tx_vid_oddeven),
        .O_rx_vid_stream_1_tx_vid_pixel0(O_rx_vid_stream_1_tx_vid_pixel0),
        .O_rx_vid_stream_1_tx_vid_pixel1(O_rx_vid_stream_1_tx_vid_pixel1),
        .O_rx_vid_stream_1_tx_vid_pixel2(O_rx_vid_stream_1_tx_vid_pixel2),
        .O_rx_vid_stream_1_tx_vid_pixel3(O_rx_vid_stream_1_tx_vid_pixel3),
        .O_rx_vid_stream_1_tx_vid_vsync(O_rx_vid_stream_1_tx_vid_vsync),
        .aux_rx_io_n(aux_rx_io_n),
        .aux_rx_io_p(aux_rx_io_p),
        .aux_tx_io_n(aux_tx_io_n),
        .aux_tx_io_n_0(aux_tx_io_n_0),
        .aux_tx_io_p(aux_tx_io_p),
        .aux_tx_io_p_0(aux_tx_io_p_0),
        .clk_100(clk_100),
        .clk_200(clk_200),
//        .clk_bl_125(clk_bl_125),
//        .clk_ddr_ref_200(clk_ddr_ref_200),
        .clk_out0(clk_out0),
        .clk_out1(clk_out1),
        .dp159_IIC_scl_i(dp159_IIC_scl_i),
        .dp159_IIC_scl_o(dp159_IIC_scl_o),
        .dp159_IIC_scl_t(dp159_IIC_scl_t),
        .dp159_IIC_sda_i(dp159_IIC_sda_i),
        .dp159_IIC_sda_o(dp159_IIC_sda_o),
        .dp159_IIC_sda_t(dp159_IIC_sda_t),
        .dp159_OE(dp159_OE),
        .locked(locked),
        .mgtrefclk0_pad_n_in(mgtrefclk0_pad_n_in),
        .mgtrefclk0_pad_p_in(mgtrefclk0_pad_p_in),
        .mgtrefclk1_pad_n_in(mgtrefclk1_pad_n_in),
        .mgtrefclk1_pad_p_in(mgtrefclk1_pad_p_in),
        .peripheral_aresetn1(peripheral_aresetn1),
        .phy_txn_out(phy_txn_out),
        .phy_txn_out_0(phy_txn_out_0),
        .phy_txp_out(phy_txp_out),
        .phy_txp_out_0(phy_txp_out_0),
        .rx_bpc(rx_bpc),
        .rx_cformat(rx_cformat),
        .rx_hpd(rx_hpd),
        .rx_vid_msa_hres(rx_vid_msa_hres),
        .rx_vid_pixel_mode(rx_vid_pixel_mode),
        .rx_vid_stream1_tx_vid_enable(rx_vid_stream1_tx_vid_enable),
        .rx_vid_stream1_tx_vid_hsync(rx_vid_stream1_tx_vid_hsync),
        .rx_vid_stream1_tx_vid_oddeven(rx_vid_stream1_tx_vid_oddeven),
        .rx_vid_stream1_tx_vid_pixel0(rx_vid_stream1_tx_vid_pixel0),
        .rx_vid_stream1_tx_vid_pixel1(rx_vid_stream1_tx_vid_pixel1),
        .rx_vid_stream1_tx_vid_pixel2(rx_vid_stream1_tx_vid_pixel2),
        .rx_vid_stream1_tx_vid_pixel3(rx_vid_stream1_tx_vid_pixel3),
        .rx_vid_stream1_tx_vid_vsync(rx_vid_stream1_tx_vid_vsync),
        .sys_rst(sys_rst),
        .tx_hpd(tx_hpd),
        
        .tx_lane0_tdata(tx_lane0_tdata),
        .tx_lane0_tready(tx_lane0_tready),
        .tx_lane0_tuser(tx_lane0_tuser),
        .tx_lane0_tvalid(tx_lane0_tvalid),
       // .tx_hpd_0(tx_hpd_0),
        .tx_video_stream0_tx_vid_enable(tx_video_stream0_tx_vid_enable),
        .tx_video_stream0_tx_vid_hsync(tx_video_stream0_tx_vid_hsync),
        .tx_video_stream0_tx_vid_oddeven(tx_video_stream0_tx_vid_oddeven),
        .tx_video_stream0_tx_vid_pixel0(tx_video_stream0_tx_vid_pixel0),
        .tx_video_stream0_tx_vid_pixel1(tx_video_stream0_tx_vid_pixel1),
        .tx_video_stream0_tx_vid_pixel2(tx_video_stream0_tx_vid_pixel2),
        .tx_video_stream0_tx_vid_pixel3(tx_video_stream0_tx_vid_pixel3),
        .tx_video_stream0_tx_vid_vsync(tx_video_stream0_tx_vid_vsync),
        .tx_video_stream1_tx_vid_enable(tx_video_stream1_tx_vid_enable),
        .tx_video_stream1_tx_vid_hsync(tx_video_stream1_tx_vid_hsync),
        .tx_video_stream1_tx_vid_oddeven(tx_video_stream1_tx_vid_oddeven),
        .tx_video_stream1_tx_vid_pixel0(tx_video_stream1_tx_vid_pixel0),
        .tx_video_stream1_tx_vid_pixel1(tx_video_stream1_tx_vid_pixel1),
        .tx_video_stream1_tx_vid_pixel2(tx_video_stream1_tx_vid_pixel2),
        .tx_video_stream1_tx_vid_pixel3(tx_video_stream1_tx_vid_pixel3),
        .tx_video_stream1_tx_vid_vsync(tx_video_stream1_tx_vid_vsync),
        
        .DP1_axi4s_rstn  (    DP1_axi4s_rstn   ),
        .DP1_phy_rstn    (    DP1_phy_rstn     ),
        .DP1_sb_aclk     (    DP1_sb_aclk      ),
        .DP1_tx_data     (    DP1_tx_data      ),
        .DP1_tx_data1    (    DP1_tx_data1     ),
        .DP1_tx_data2    (    DP1_tx_data2     ),
        .DP1_tx_data3    (    DP1_tx_data3     ),
        .DP1_tx_link_clk (    DP1_tx_link_clk  ),
        .DP1_tx_ready    (    DP1_tx_ready     ),
        .DP1_tx_ready1   (    DP1_tx_ready1    ),
        .DP1_tx_ready2   (    DP1_tx_ready2    ),
        .DP1_tx_ready3   (    DP1_tx_ready3    ),
        .DP1_tx_user     (    DP1_tx_user      ),
        .DP1_tx_user1    (    DP1_tx_user1     ),
        .DP1_tx_user2    (    DP1_tx_user2     ),
        .DP1_tx_user3    (    DP1_tx_user3     ),
        .DP1_tx_valid    (    DP1_tx_valid     ),
        .DP1_tx_valid1   (    DP1_tx_valid1    ),
        .DP1_tx_valid2   (    DP1_tx_valid2    ),
        .DP1_tx_valid3   (    DP1_tx_valid3    ));
        
        
        
  IOBUF dp159_IIC_scl_iobuf
       (.I(dp159_IIC_scl_o),
        .IO(dp159_IIC_scl_io),
        .O(dp159_IIC_scl_i),
        .T(dp159_IIC_scl_t));
  IOBUF dp159_IIC_sda_iobuf
       (.I(dp159_IIC_sda_o),
        .IO(dp159_IIC_sda_io),
        .O(dp159_IIC_sda_i),
        .T(dp159_IIC_sda_t));
endmodule
